A phase-locked loop (PLL) typically includes an oscillator known as a voltage controlled oscillator (VCO), a phase detector (or Phase Frequency Detector, PFD), and a loop filter. The output of the VCO is compared with a reference signal in the phase detector or PFD. The output of the phase detector is filtered in the loop filter to create a control voltage. The frequency of the VCO is adjusted by the control voltage until the output of the VCO and the reference signal have a particular phase relationship.
A VCO output may be divided in frequency to obtain a desired frequency. Some PLLs include a dividing circuit that divides the output of the VCO. Such a dividing circuit may have a configurable dividing factor. However, such a dividing factor is typically set during calibration, testing, manufacturing, or the like, and is not subsequently changed.
As a result, the output frequency range of such a PLL is limited to the frequency range of the VCO as divided by the fixed dividing factor. Furthermore, if the dividing factor and other characteristics of the VCO are calibrated or configured, additional test time is required. In addition, for some products such as a zero delay buffer, a frequency of the reference signal is not known in advance. Thus, the calibration or selection of a dividing factor for a particular reference signal may not be performed.
Accordingly, there remains a need for an improved phase locked loop.